Field Programmable Logic Gates Using GMR Devices*

Introduction

The usage of GMR devices so far has been limited to sensors, non-volatile memory and disk drive read heads. However, the fact that these devices exhibit a digital behavior lends them to the building of logic gates. Furthermore, due to the simplicity of changing the resistance setting (digital value) of a GMR device, this technology is suitable as field programmable logic devices (FPLDs).

The physical and magnetic descriptions of GMR memory devices can be found in [1] and [2]. For this purely digital application, a simple schematic symbol and model for the device are shown in figure 1. While the techniques presented here are applicable to many GMR bit configurations, for this figure, an asymmetrical GMR sandwich film ("pseudo spin-valve") has been assumed.

Figure1: Schematic and model for basic GMR element

The definitions for high and low logic values presented herein and used throughout this paper are arbitrary and are changeable to suit the particular GMR technology being used. Given a positive word current (Iw) in the range of 1-5 mA, the resistance of the device is approximately R+dR if it is programmed high and is approximately R if programmed low. dR is defined as shown in figure 1. If a negative word current is applied, again in the range of 1-5 mA, then the resistance of a device programmed high is R and the resistance of a device programmed low is R+dR. Depending on the GMR technology, the resistance change at Iw=0 can be very close to the values when a positive Iw is applied. So by definition, a logic 1 input to this device is represented by a small positive word current, and a logic 0 input is represented by a small negative word current. A device is programmed high or low by simply applying a large negative or positive (approximately 25mA) word current, respectively. This makes the device very easily programmable in the field.

Basic FPLD structure

A basic voltage sensing** FPLD structure is shown in figure 2 and will be referred to as a gate, and each GMR device will be referred to as a bit. For the sake of illustration, a 4-input gate is shown and will be analyzed. The bottom bit of each pair is the evaluation bit and the top bit is the reference bit. Programming the reference bit high or low configures the logic function of the gate and programming the evaluation bit high or low includes or excludes that particular input from the gate. The maximum number of inputs a gate can have is dependent on the process and GMR device size. With existing auto-zero techniques applied in MRAM memories[3], gate configurations of up to 60 inputs appears possible.

Figure 2: Basic field programmable circuit

Using a mixture of Boolean expressions and mathematical expressions, the differential input of the amplifier for the above FPLD configuration can be written as

where Bi and Bri are the programmed values of the ith evaluation and reference bits, respectively, (1 or 0 for high or low), Xi and Xri are the logic value on the inputs to the evaluation and reference bits, respectively (1 or 0),Vos is the input offset voltage on the sense amp and is the signal threshold needed to trip the sense amp. For example, the FPLD in figure 2 may be programmed as a 2-input through 4-input NOR gate by programming all the bits in the reference leg high and setting the Xri's to 1. Bi is set to 1 if input i is to be included in the evaluation. The logic value of the gate therefore becomes:

Assuming all Xri's are 1, other logic functions can be programmed as follows: NAND: Bi low and Bri high; OR: Bi low and Bri low and AND: Bi high and Bri low. More random logic functions can be built by mixing and matching the programming of the bits.

Conclusions

This paper summarizes the basic methodology for building field programmable logic functions using GMR devices. The size of the gates and the properties of the sense amplifier are a function of the particular GMR technology used, device matching and the magnitude of the sense current available. A test chip is currently in fabrication.

**Several sensing schemes are possible, e.g. tying the left end of the string to a voltage source and sensing the current. Due to the page limitation,only a voltage sensing scheme is presented.

References