Cadence Software Tools at EE/CprE

ISU Cadence Homepage| Site Map | Help Page | ISU EcpE Homepage | ISU Homepage

Electrical and Computer Engineering Department at Iowa State University

Member of the Cadence North America University Software Program

Overview

This page contains information about the Cadence^TM tools installed on HP^TM systems in Electrical and Computer Engineering Department at Iowa State University, Ames.

Our Configuration

Server configuration: HP 9000 C-class Model C100 with PA7200 PA-RISC at 100 MHz running HP-UX version 10.20
Workstation Clusters: HP C180, HP C240, and HP C360 Workstations

Why Cadence?

Cadence tools are chosen as the EDA tools for our VLSI design courses because of the following reasons:

Cadence offers an integrated EDA solution which encompasses the entire design flow from behavioral modeling to post-layout simulation.
The North America University program offers low-cost support and licensing.
Use of Cadence software offers ISU students experience and training with commercial-grade EDA tools.

Recent News

In May 1999, ISU transitioned from Cadence version 4.4.1 to version 4.4.3. Adjustments and modifications are ongoing. |Back to top|

ISU Cadence Contacts

Questions regarding Cadence tools installed or VLSI courses taught in our department, please e-mail our coordinator, Dr. Bill Black.
Questions regarding the maintenance and operation of the HP-UX system, please e-mail our Systems Admin .
Questions regarding the configuration and management of Cadence-related software, please e-mail our Cadence Admin. Questions about this page, please e-mail webpage administrator.

|Back to top|

Tools Actively Used by ISU Students for Coursework and Research

Digital VLSI Design
- Verilog-XL: Behavioral VHDL
  - Verilog Switch-RC: Digital design simulation
- simWaves: Digital waveform viewer
- Composer: Schematic design editor
- Virtuoso: Layout design editor
  - Virtuoso Compactor: Symbolic layout design compactor
- Diva: Physical layout verification
- Dracula: Physical layout verification
- Cell Ensemble: Pad place & route
Analog/Mixed Signal VLSI Design
- Composer
- Analog Artist: Integrated simulation environment
- Spectre / SpectreHDL
- HSpice: SPICE Modeling and simulation
- Cadence SPICE
- Waveform Display
- Virtuoso
- Diva

Tools Currently Being Installed and Customized

Cell Ensemble
Signal Processing Worksystem (SPW)
Allegro
Concept
Leapfrog (VHDL Simulator)

|Back to top|

ISU Value-Added Items for Cadence

Installation / Maintainance Guides

Locally Customized Utilities for versions 4.3.4, 4.4.1, and 4.4.3

isuMisc.il: Various SKILL code procedures.
editorPref.il: A CIW menu command to select text editor of choice.
compactLib.il: A Library Browser menu command used to compact a design library.
Technology Code is added to library property to prevent an incorrect technology file from being loaded when updating a design library's technology.
createLibISUTech.il: An enhancement to the Create Library form. It includes the Technology Code when creating a new design library. This must be configured and loaded in your isuTechMaster.il.cdsinit configuration file.
updateLibTech.il: A Library Browser menu command used to update a design library based on Technology Code. This must be configured and loaded in your isuTechMaster.il.cdsinit configuration file.
isuMenu.il: Example SKILL code explaining how to create a pull-down menu in the CIW menubar.
cdsinit_example.il: How to configure the .cdsinit configuration file for the above customizations.
rs_orbit20.v: Verilog Switch-RC NMOS and PMOS models characterized for MOSIS Supertex (formerly Orbit) 2.0u N-well (SCNA20 - N78K) process technology.
rs_ami12.v: Verilog Switch-RC NMOS and PMOS models characterized for MOSIS AMI 1.2u N-well (SCN16 - N66C) process technology.
CIFIX.c: Bug-fix post-processor for CIF files generated by Cadence PIPO 4.3.4.

(Originally written by Larry Dennison. Modified user-interface by Hon-Chi Ng

Disclaimer These SKILL utilities have been created for uses in the ECpE Department of Iowa State University. They are provided with goodwill to the general public for academic reference. The author(s) and Iowa State University are not liable for any consequences from using these utilities, i.e. they come without any warranty. If you find any bugs in the utilities, please inform the Cadence administrator.

|Back to top|

Tutorials and Design Flows

(Based on the Cadence Tools of Version 4.3.4)

CprE 465 Lab Handouts (Digital VLSI Design and Methodology -- by Hon-Chi Ng)

Tutorial Lab 1: Behavioral Modeling & Simulation (DFII, Verilog-XL, cWaves)
Tutorial Lab 2: Schematic Entry & Hierarchical Design (Composer, Verilog-XL, cWaves)
Tutorial Lab 3: Transistor Logics & Switch-Level Simulation (Composer, Verilog Switch-RC, cWaves)
Tutorial Lab 4: Polygonal Layout & Layout Verification (Virtuoso, Diva, Verilog Switch-RC)
Tutorial Lab 5: Symbolic Layout & Layout Compaction (Virtuoso Compactor, Diva, Verilog Switch-RC)
Design Lab 6: 4-Bit Bidirectional Shift Register (Block Ensemble for Pad Place & Route)

Help Pages

(Based on the Cadence Tools of Version 4.3.4)

ISU VLSI Design Help Page (by Jeff Echtenkamp)

Top 10 Cadence Hints

Online Course Lab Instructions

Laboratory Homepages with Cadence Tools Info

Cpr E 465(Fall 1997 -- lab by Hon-Chi Ng)
Cpr E 465 (Fall 1996 -- lab by Hon-Chi Ng)

|Back to top|

Course Materials

Class Homepages for VLSI Courses

Digital VLSI Courses

Cpr E 465 VLSI: Basic Layout and Design (Fall 1998 -- by Dr William Black)
Cpr E 465 VLSI: Basic Layout and Design (Spr 1998 -- by Dr Marwan Hassoun)

Cpr E 465

Fall 1997 -- by Dr William Black

Cpr E 566 Design of VLSI Systems (Fall 1997 -- by Dr Marwan Hassoun)

Analog/Mixed Signal VLSI Courses

E E 434 Analog Integrated Circuits I
E E 435 Analog Integrated Circuits II
E E 501 Analog VLSI Circuit Design
E E 505 CMOS and BiCMOS Data Conversion (Spr 1998 -- by Dr William Black)

Research

Analog and Mixed-Signal VLSI Design

Other Cadence-Related Resources

|Back to top|

Please use this information at your own risk -- and any attempt to use this information IS at your own risk -- we recommend using it on a copy of your data to be sure you understand what it does. Keep your master intact until you are personally satisfied with the use of this information within your environment.

Maintained by: Cadence Admin( cdsmgr@dsdl.ee.iastate.edu)
Last Modified on Thursday, 24-February-2000 14:30:00 CST
Access Count: Accessed times since November 11, 1998
At URL: http://vlsi.ee.iastate.edu/~hcng/cadence-WWW/index.shtml